Flat no-lead packages with electroplated edges

ABSTRACT

A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Divisional of and claims benefit to U.S. patent application Ser. No. 14/842,460, file Sep. 1, 2015, which is incorporated herein by reference in its entirety.

FIELD

Disclosed embodiments relate to flat no-lead semiconductor packages and assembly processes for such packages.

BACKGROUND

A variety of semiconductor chip packages are known that provide support for an integrated circuit chip (IC) or die and associated bond wires, provide protection from the environment, and enable surface mounting of the die to and interconnection with a printed circuit board (PCB). One conventional package configuration is a flat no-leads package such as quad-flat no-lead (QFN) or and dual-flat no-lead (DFN). Flat no-lead packages, also known as micro leadframe (MLF) and SON (small-outline no leads), is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Perimeter lands or terminals exposed on the package bottom provide electrical connections to the PCB. Flat no-lead packages also include an exposed thermal die pad to improve heat transfer out of the IC (into the PCB).

QFNs and DFNs are relatively difficult to solder to because all the terminal connections are on the bottom of the package. Some designs have small extensions for these terminals that wrap around the bottom corner of the package and come up along the edge of the package somewhat. As QFN and DFN packages conventionally comprise copper leadframes, to allow soldering thereto they have added terminal finishes, such as comprising Matt Sn (100% tin) which is applied to the terminals using an electroless (or auto-catalytic by only chemical means) plating process. The QFN/DFN tin coated terminals can then be soldered to a PCB.

Inspection of QFN and DFN packages soldered onto a PCB is typically done with X-ray equipment for an assembly process monitor. The X-ray can detect solder bridging, shorts, opens, voids and solder joint fillets under the leads and exposed pads which are determined as the critical area of termination. For example, the J-STD-002C solderability standard includes a proposed (in ballot) soldering criteria for the QFN/DFN. Some customers (e.g., automotive customers) for QFN packaged semiconductor devices besides requiring a terminal underside solder inspection also require a side solder inspection.

SUMMARY

This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.

Disclosed embodiments recognize the use of electroless 100% Sn (tin) for terminal finishes for flat no-lead packages (QFN or DFN) is susceptible to the phenomenon known as tin whiskering. Tin whiskers are known to be electrically conductive single crystal tin eruptions that can grow from surfaces where tin is deposited on a substrate surface, typically being 1 μm to 5 μm in diameter and between 1 μm and 500 μm in length. Such whiskers can cause shorting (e.g., whisker bridging) that reduces yield and can cause reliability problems. Disclosed embodiments recognize an electrolytic (electroplating) terminal finishing process instead of a conventional electroless plating process would remove Sn whiskering, however the need for electrical contact to all surfaces to enable electroplating to take place on all such surfaces eliminates the possibility of using conventional electroplating.

Disclosed methods overcome this barrier to electroplating a terminal finishing metal with an electroplating method by including a removably shorting together step that shorts together all surfaces to be plated which enables electroplating a metal or metal alloy finish onto the QFN/DFN terminals including their edges of a packaged semiconductor device. Disclosed methods include a first partial saw process that exposes sides of the package terminals, followed by removably shorting together (e.g., using a jig or wire bonds) to electrically connect together all the surfaces to be electroplated, removing of the shorting together, and a second sawing step that finishes sawing through the plastic encapsulation to provide singulation to form a plurality of packaged semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:

FIG. 1 is a flow chart that shows steps in an example method for forming electroplated terminal finishes including electroplated edges for flat no-lead packages, according to an example embodiment.

FIG. 2A is a backside and a cross section view of a panel of in-process flat no-lead packages after plastic encapsulation, and FIG. 2B is a cross section view of a single unit from the panel, according to an example embodiment.

FIGS. 3A and 3B is a backside and a cross section view of a panel of in-process flat no-lead packages after backside partial sawing, respectfully, according to an example embodiment.

FIG. 4 is a cross section view of a panel of in-process flat no-lead packages after backside wirebonding, according to an example embodiment.

FIG. 5A is a cross section view of a panel of in-process flat no-lead packages after electroplating the terminals along with their edges, according to an example embodiment.

FIG. 5B is a cross section view of a panel of in-process flat no-lead packages after electroplating the terminals along with their edges with 2 plating layers, according to an example embodiment.

FIG. 6 is a cross section view of a panel of in-process flat no-lead packages depicting the shearing off the wirebonds without damaging the plating layer on the terminals, and the resulting wirebond contact regions on the exposed thermal die pad (exposed thermal pad) and back side of the terminals which lack the plating layer, according to an example embodiment.

FIG. 7A is a cross section view of a panel of in-process flat no-lead packages depicting the result after finishing with a smaller saw that runs all the way through the plastic encapsulation to provide package singulation with 3 singulated package units shown.

FIG. 7B is a cross section view of a panel of one of the singulated package units shown in FIG. 7A inverted 180 degrees.

DETAILED DESCRIPTION

Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.

Also, the terms “coupled to” or “couples with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “couples” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.

FIG. 1 is a flow chart that shows steps in an example method 100 for forming electroplated terminal finishes including electroplated edges for packaged flat no-lead packages, according to an example embodiment. Step 101 comprises providing a lead frame sheet (or lead frame panel) including a plurality of joined flat no-lead lead frames (lead frames) each having a semiconductor die including bond pads thereon mounted on a die pad with bond wires between the bond pads and terminals of the lead frames.

The lead frames typically comprise copper or a copper alloy. Plastic encapsulation is included except on a back side of the lead frame sheet to expose a back side of the die pad to provide an exposed thermal pad and to expose a back side of the terminals. The lead frames can comprise quad-flat no-lead (QFN) or dual-flat no-lead (DFN). FIGS. 2A and 2B show a backside view of a panel 200 showing six (6) in-process flat no-lead packages after plastic encapsulation showing the plastic 211, and the exposed die pad 205 and exposed terminals 208, and FIG. 2B shows a cross section view of a single unit 250 from the panel, according to an example embodiment. Saw lanes for step 102 described below are shown as 213. The semiconductor die is shown as 225 and the die attach material (e.g., an epoxy) as 226. Bond wires 229 are shown connecting bond pads on the top surface of semiconductor die 225 to the terminals 208.

Step 102 comprises partial sawing in the saw lanes beginning from the back side through the terminals ending with saw lines having a line width terminating within the plastic encapsulation to provide exposed side walls of the terminals and exposed side walls of the plastic encapsulation. The partial sawing can comprise mechanical sawing or laser sawing. FIGS. 3A and 3B show backside and a cross section view, respectively, of a panel 300 of in-process flat no-lead packages after backside partial sawing using the saw lanes 213 shown in FIG. 2A to form saw lines 310, according to an example embodiment.

Step 103 comprises shorting together (e.g., using a jig (essentially a bed of nails), jumper, or wire bonding) all the exposed thermal pad(s) and exposed back side of the terminals to form electrically interconnected metal surfaces (interconnected surfaces). FIG. 4 is a cross section view of a panel 400 of in-process flat no-lead packages after backside wirebonding, according to an example embodiment. Wirebonds to provide the electrically interconnected surfaces are shown as bond wires 429.

Step 104 comprises electroplating the interconnected surfaces with a solder wetable metal or metal alloy plating layer on the back side and on the exposed side walls of the terminals. Electroplating as known in the art is a process that uses electrical current from a power supply to reduce dissolved metal cations in a plating solution so that they form a metal coating on the desired surface to be plated that is configured as a cathode. FIG. 5A is a cross section view of a panel 500 of in-process flat no-lead packages after electroplating a plating layer 520 on the terminals being the exposed die pads 205 and exposed terminals 208, according to an example embodiment.

Although the plating layer 520 is shown as a single layer, the plating layer can comprise a stack of different plating layers, such as the stack of plating layers in one particular embodiment being NiPdAu (3 layers). FIG. 5B is a cross section view of a panel of in-process flat no-lead packages after electroplating the terminals along with their edges with 2 plating layers shown 520 b on 520 a, according to an example embodiment. Because of the bond wires 429 or other shorting structures being present during the electroplating the exposed thermal pad 205 and back side of the terminals 208 each include a contact region (see contact region 615 shown in FIG. 6) having an area of about that of the bond wire which lacks the plating layer. The contact region is generally 0.8 mil (0.0206 mm) to 5 mil (0.127 mm) in diameter, and is typically 1 to 2 mils in diameter.

Step 105 comprises decoupling the interconnected surfaces. When the shorting together comprises using bond wires, the decoupling can comprise using a metal brush for shearing off the bond wires. In the case of a jig, the jig is lifted up to remove the contacts of its nails or probes with the terminals. FIG. 6 is a cross section view of a panel 600 of in-process flat no-lead packages depicting the shearing off the bond wires 429 without damaging plating layer 520 on the terminals, according to an example embodiment. The exposed thermal pad 205 and back side of the terminals 208 can be seen to each include a contact region 615 which lacks the plating layer 520.

Step 106 comprises a second sawing in the saw lanes to finish sawing beginning from the bottom of the saw lines through the plastic encapsulation 211 to provide singulation to form a plurality of packaged semiconductor devices. FIG. 7A is a cross section view of a panel 700 of in-process flat no-lead packages depicting the result after finishing with a smaller saw that runs all the way through the plastic encapsulation 211 to provide package singulation with 3 singulated package units shown. FIG. 7B is a cross section view of a panel of one of the singulated package units shown in FIG. 7A identified as 750 inverted 180 degrees to have its top side up.

Advantages of disclosed methods and packaged semiconductor devices therefrom include the elimination of tin whiskering. Side wetting is also provided to enable a visual solder inspection instead of having to conventionally rely on an x-ray inspection for electrolytic processes.

Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor integrated circuit (IC) devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as package on package (PoP) configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure. 

1-16. (canceled)
 17. A packaged semiconductor flat no-lead device, comprising: a flat no-lead lead frame having a semiconductor die including bond pads thereon mounted on a die pad of said lead frame with bond wires between said bond pads and terminals of said lead frame, and plastic encapsulation except on a back side of said lead frame to expose said die pad to provide an exposed thermal die pad and to expose a back side of said terminals and side walls of said terminals; a solder wetable metal or metal alloy plating layer on said back side and on said exposed side walls of said terminals; wherein said exposed thermal die pad and said back side of said terminals each include a contact region which lacks said plating layer.
 18. The packaged semiconductor device of claim 17, wherein said plastic encapsulation is at a first width on a top portion of said packaged semiconductor device and at a second width at a bottom of said packaged semiconductor device, and wherein said first width is greater than said second width to provide a side wall step along an edge of said plastic encapsulation.
 19. The packaged semiconductor device of claim 17, wherein said lead frame comprises a quad-flat no-lead (QFN) or a dual-flat no-lead (DFN).
 20. The packaged semiconductor device of claim 17, wherein said lead frame comprises copper or a copper alloy.
 21. The packaged semiconductor device of claim 17, wherein said plating layer comprises a stack of a plurality of different ones of said plating layer.
 22. The packaged semiconductor device of claim 21, wherein said stack comprises nickel (Ni)-palladium (Pd)-gold (Au).
 23. The packaged semiconductor device of claim 17, wherein said contact region is 0.8 mil (0.0206 mm) to 5 mil (0.127 mm) in diameter. 